1. Field of the Invention
The present invention relates in general to an MPEG-2 system decoder, and more particularly to a clock recovery circuit and method for the MPEG-2 system decoder.
2. Description of the Prior Art
An MPEG-2 system decoder divides into two kinds that is, a program system decoder for separating audio and video data from a program stream of storing means, for example a CD ROM, and a transport stream decoder for separating audio and video data from a transport stream of a broadcasting signal.
An MPEG-2 system encoder encodes audio and video data, respectively, and packetizes the encoded audio and video data. Then, the MPEG-2 system encoder multiplexes the packetized data into a program stream or a transport stream to be transmitted.
FIGS. 1a and 1b are views illustrating data formats of the program and transport streams, respectively. As shown in FIG. 1a, the transport stream is composed of an audio or video packet which has a packet header at its head portion. As shown in FIG. 1b, the program stream is composed of a pack which includes a plurality of audio and video packets and has a pack header at its head portion (see ISO/IEC 13818-1, Annex F).
The packet header of the transport stream includes a program clock reference (PCR), and the pack header of the program stream includes a system clock reference (SCR). The PCR and SCR are information for correcting a system clock frequency, which is a time reference of an MPEG-2 system decoder, into a value intended by the encoder.
FIG. 2 is a detailed diagram of the data format of the transport stream in FIG. 1a. As shown in this drawing, each transport stream packet has a capacity of 188 bytes and consists of two parts a packet header and a payload. The packet header consists of a packet header part of 4 bytes and a variable length adaptation field part. The variable length adaptation field part includes a PCR of 48 bits and various other information. The PCR includes a PCR base part of 33 bits, a reserved part of 6 bits and a PCR extension part of 9 bits. Disregarding reserved bits, the PCR is 42 bits-long (see ISO/IEC 13818-1, Table 2-b).
Although not shown, the pack header of the program stream includes an SCR which is composed of 42 bits in the MPEG-2 system (see ISP/IEC 13818-1, Annex F.0.7).
The reason why the PCR and SCR are composed of 42 bits, respectively, is for representing the range of 24 hours at 27 MHz. Namely, the 9-bit PCR extension part is used to count from 0 to 299 repeatedly at 27 MHz, and the 33-bit PCR base part is used to count by one whenever the counting operation is performed from 0 to 299 at the 9-bit PCR extension part. In this manner, the range of 24 hours can be represented at 27 MHz. In this case, the 33-bit PCR base part has a value counted at 90 KHz.
As mentioned above, the PCR and SCR are used to correct the STC, which is the time reference of the MPEG-2 system decoder, into a value intended by the encoder. The MPEG-2 system decoder comprises a phase locked loop (PLL) for the synchronization with the PCR and SCR (see ISO/IEC 13818-1. Annex D.0.3 for MPEG-2 recovery method). The use of the PLL allows the STC to be in perfect accord with a system clock of the encoder in frequency. The system clock of the encoder is 27 MHz in the MPEG-2 system, and the STC of the decoder is compared with a decoding time stamp (DTS) and a presentation time stamp (PTS) so that audio and video frames can be decoded and reproduced accurately at times determined by the encoder. Namely, the PTS is information for the control of a reproducing time and the DTS is information for the control of a decoding time. The PTS and PCR/SCR base parts are used to represent a value counted at 90 KHz as a 33-bit length. The reason why the frequency is 90 KHz is that it is a common multiple of video frame frequencies in NTSC and PAL systems and for obtaining a precision degree higher than that of an audio sample period (44.1 KHz).
Conventionally, upon receiving the transport or program stream from the encoder, the decoder detects the PCR or SCR therefrom for the clock synchronization. Then, the decoder sets the first PCR or SCR as the STC and performs a phase locked operation so that a system clock of the decoder can be in accord with the system clock of the encoder. In the MPEG-2 system decoder, an apparatus for performing the phase locked operation to restore the system clock of the decoder to the system clock of the encoder is called a clock recovery circuit (ISO/IEC 13818-1. FIG. D-2).
A conventional clock recovery circuit for the MPEG-2 system decoder must employ a 42-bit counter for generating a 42-bit STC for the comparison with the 42-bit PCR or SCR. For this reason, a data access time becomes longer in the case where a 16-bit or 32-bit digital signal processor is used for the clock recovery. For example, in the case where the 32-bit digital signal processor is used to access 42-bit data, it has to perform the data access operation twice. That is, since the 32-bit digital signal processor consists of 32-bit ALU, it is necessary more dummy cycles to access 42-bit data. This causes the processor to deteriorate its processing effects although the processor must perform a demultiplexing operation of bitstream being continuously received at high speed. The conventional clock recovery circuit has a further disadvantage that, if the first PCR or SCR is received upon power-on or channel change, it should be set in the 42-bit counter.
However, considering the fact that an input period of the PCR is 0.1 sec and an input period of the SCR is 0.7 sec, there is no necessity for comparing all of the 42 bits of the PCR or SCR with the 42 bits of the STC. In other words, the 42-bit counter is not necessary.
FIG. 3 is a block diagram of a conventional clock recovery circuit for MPEG-2 system decoder. As shown in this drawing, the conventional clock recovery circuit comprises a digital signal processor 300 including a controller 310, a PCR/SCR detector 320, an adder/subtracter unit 330 and a digital filter 340, a digital/analog converter (DAC) 350, a low pass filter 360, a voltage controlled oscillator 370 and a 42-bit counter 380. In FIG. 3, a digital signal processor included generally in the MPEG-2 system decoder is shown to be used for the clock recovery.
Upon receiving a transport or program stream, the PCR/SCR detector 320 detects a 42-bit PCR or SCR therefrom. The controller 310 receives the PCR or SCR detected by the PCR/SCR detector 320 and then checks whether the received PCR or SCR is an initial value. If the received PCR or SCR is the initial value, the controller 310 transfers the received PCR or SCR to the 42-bit counter 380 to set it in the 42-bit counter 380. However, in the case where the received PCR or SCR is not the initial value, the controller 310 transfers the received PCR or SCR to the adder/subtracter unit 330 which then subtracts an STC, which is an output value from the 42-bit counter 380, from the transferred PCR or SCR. The digital filter 340 digital-filters an output value from the adder/subtracter unit 330 to generate a 16-bit digital value. The DAC 350 converts the digital value from the digital filter 340 into an analog value. The low pass filter 360 low pass filters the analog value from the DAC 350. The voltage controlled oscillator 370 generates a system clock reference which is varied in frequency according to an output value from the low pass filter 360. Namely, in the case where the output value from the adder/subtracter unit 330 is positive, it is signified that the system clock is low in frequency. In this case, the voltage controlled oscillator 370 generates the system clock at a higher frequency. However, in the case where the output value from the adder/subtracter unit 330 is negative, it is signified that the system clock is high in frequency. In this case, the voltage controlled oscillator 370 generates the system clock at a lower frequency. On the other hand, after being set to the initial PCR or SCR, the 42-bit counter 380 performs a counting operation in response to the system clock from the voltage controlled oscillator 370. Differently from the general counting operation, the 42-bit counter 380 generates the lower-order 9 bits by repeatedly counting from 0 to 299 and the higher-order 33 bits by counting by one whenever counting from 0 to 299,. Then, the 42-bit counter 380 outputs the counted value to the adder/subtracter unit 330.
However, in the above-mentioned conventional clock recovery circuit for the MPEG-2 system decoder, if the PCR or SCR of the transport or program stream is the initial value, it must be set in the 42-bit counter. Also, the 42-bit counter is used to generate the 42-bit STC for the comparison with the 42-bit PCR or SCR. For this reason, a data access time becomes longer in the case where a 16 bit or 32-bit digital signal processor is used to access 42-bit data. For example, in the case where the 32-bit digital signal processor is used to access 32-bit data, it performs the data access operation only once. However when the 32-bit digital signal processor accesses 42-bit data, it has to perform the data access operation twice. However, considering input periods of the PCR and SCR, there is no necessity for comparing all of the 42 bits of the PCR or SCR with the 42 bits of the STC.
In result, the above-mentioned conventional clock recovery circuit is disadvantageous in that the data access time becomes longer in the case where the 16-bit or 32-bit digital signal processor is used to access 42-bit data, and the STC must be changed to the initial PCR or SCR whenever the initial PCR or SCR is received.